Clock and data recovery/Buffer Memory (Elastic Buffer)/Overflow and Underflow
Overflow and Underflow
Two clocks that differ slightly in frequency (=that wander) with respect to each other, or that jitter significantly with respect to the one another, will -from time to time- change their respective positions cumulating more phase difference than the buffer can absorb. The slower clock does “slip” with respect to the other and the period that it loses is a “slip”. When the reading (reading clock faster than the writing clock) takes place synchronously or before the corresponding writing cycle, then an underflow occurs (with a repetition of some information elements). If instead this condition is approached because the reading clock is too slow with respect to the writing clock, then an overflow occurs (and some information elements are skipped = cancelled). In case of over/underflow, the reading counter is reinitialised, half a memory behind the write clock (to restart with the maximum margin against another future occurrence).
- Figure 2 above shows a case where two different clocks (the system clock and its copy after many regenerations) are to be re-synchronised together. This is not the most general case, because the two clocks represented here belong to the same clock domain (i.e. are generated from the same clock, apart from fixed delay and jitter).
- If two clocks that do not share a link with a common clock source (=they belong to different clock domains) and are to be reconciled (by an elastic buffer), then the thing is complicated by the fact that, in addition to jitter, they exhibit a frequency difference ( a wander), although small.
- If an elastic buffer, of depth equal to n clock cycles, is at the boundary between different clock domains of frequencies f1 and f1-Δf, it will be subject to periodic slips (under or overflows), with a frequency given by:
- Deliberate Slips (overflow or underflow execution with minimum inconvenience to the “payload”)
- In some cases, when the incoming data flow is framed, if a slip is inevitable it may be convenient to slip (cancel or replicate) an entire frame, exactly from beginning to end (e.g. TDM frames of layer 1 synchronization).
- Or, if the incoming data have a layer 2 packet structure, it may be convenient to drop or duplicate inter-frame idle characters (e.g. Ethernet inter-frame characters). To do so, when the reading clock gets close (e.g. within +/- 5% of the buffer size) to the writing clock and a slip appears inevitable within a short time, the decision to slip is taken, but it is put to effect a little later, in coincidence with the start of the next frame. Obviously, the buffer must be long at least 10% more than one entire frame.
- The cost is not significantly different whether the buffer memory is organised by bit or by byte. The saving in transit time when organising by bit with respect to organising by byte, is not significant either, as the average delay is expected to be several bytes.